An instruction cache sometimes stores predecoded instructions defined by an internal instruction set architecture (ISA), which may differ substantially from the standard instruction set (e.g., assembly language) a programmer uses to direct the operations of a processor. For example, the instructions in the cache may have additional bits with meanings not found in the standard instructions. In some systems, these additional bits may be derived from the bits present in the instruction itself; in others, from the address of the instructions.
When an access causes a cache miss, a request for a block of memory containing the instructions is sent to the memory system (which may include other caches). As the requested block of memory is returned, it passes through predecode logic that transforms the included instructions to an internal, predecoded form.
Some ISAs permit operation in a number of different modes, wherein each mode is associated with a potentially different set of transforms in the predecode logic. Examples include the Thumb® and ARM® instruction sets that are part of the XScale™ technology available from Intel Corporation of Santa Clara, Calif. In some modes the instructions sent to the predecoder are of a different width than in other modes, which can create implementation problems.
For example, since 16-bit Thumb® instructions may be predecoded into the same internal ISA used by 32-bit ARM® instructions, a block of internal-format instructions derived from a particular block of Thumb® instructions may require twice the space of the internal-format instructions derived from the same size block of ARM® instructions. It is also possible for both ARM® or Thumb® instructions to reside in any block of memory larger than 6 bytes, which means that a block of instructions fetched from memory may be a mix of both ARM and Thumb instructions. Therefore, determining which predecoder to use for a cache fill may not be feasible by simply analyzing data returned from the memory system, or knowing from where in the memory system the data was returned. Finally, some instructions can only be executed in privileged modes. Installing additional privilege-checking logic to determine the existence of illegally-fetched instructions may enlarge the execution pipeline, slowing execution speed and increasing power usage.